1. Technical Field
The present invention relates to a test apparatus. More particularly, the present invention relates to a test apparatus that is capable of acquiring the logic value of a response signal output from a device under test without the influence of a test signal that is supplied to the device under test.
2. Related Art
A semiconductor integrated circuit such as an IC or LSI is tested by a test apparatus that inputs a predetermined test signal into the device under test, measures a response signal correspondingly output from the device under test, and judging the acceptability of the device under test based on the result of the measurement. Such a test apparatus can test whether the device under test operates normally by judging whether the logic pattern of the response signal that is output from the device under test in response to receiving the test signal that is generated based on a test pattern matches an expected value corresponding to the test pattern.
According to the test apparatus disclosed in Japanese Patent Application Publication No. 2006-023233, for example, the main part of the test apparatus is connected to a device under test in a so-called single transmission wiring fashion. Accordingly, a test signal input into the device under test propagates through the same transmission line as a response signal output from the device under test.
The above-described test apparatus may perform a test on a device under test in such a sequential manner that a test signal is input into the device under test and a response signal is then received from the device under test, for example. In this case, the response signal output from the device under test may be superimposed with a test signal to be subsequently input into the device under test, and the test apparatus may detect the resulting superimposed response signal. The above-described test apparatus, however, cancels the components of the test signal from the response signal, thereby accurately detecting the response signal output from the device under test. Unfortunately, this test apparatus disadvantageously has a complicated circuit structure due to a circuit that compares a to-be-detected signal with a comparison signal and generates the comparison signal.